Multicore Programming | Session 3: Caches, Coherency and Cache-Aware Software

Multicore Programming | Session 3: Caches, Coherency and Cache-Aware Software

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What must a coherent cache system guarantee, and how do you prove those guarantees before writing software that depends on them?

This session covers cache hierarchies, the MESI coherency protocol, UVM scoreboards, formal verification and directory-based coherency for systems with 16 or more harts.

You will explore the five-phase cache subsystem integration process, TileLink and Chipyard, followed by cache-aware software techniques involving data layout, false sharing, producer-consumer fences and lock-free single-producer/single-consumer (SPSC) queues.

The session also introduces the measure, optimize, re-measure and verify workflow for investigating software performance while preserving correctness.

This session is part of a six-session professional training programme:

• Session 1 — Multi-Hart Verification and RVWMO

• Session 2 — HARTBREAKER and the Confirmed Bugs

• Session 3 — Caches, Coherency and Cache-Aware Software

• Session 4 — SoC Integration and Multicore Software

• Session 5 — Virtual Memory and Hypervisors

• Session 6 — Application-Domain SoCs and Sign-Off

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• Cache hierarchy and the MESI protocol

• UVM scoreboards for tracking memory writes

• Formal coherency verification using SVA, Murphi, TLA+ and JasperGold

• Directory-based coherency for 16 or more harts

• The five-phase cache subsystem integration process

• TileLink and Chipyard

• Cache-aware software data layout

• False sharing and cache-line padding

• Producer-consumer synchronization fences

• Lock-free SPSC queues

• Performance measurement and verification

Why This Matters

Cache coherency must guarantee correct behaviour when multiple processors access shared data. Software performance also depends on how data is arranged in memory and how synchronization is implemented.

This session connects formal verification of cache behaviour with practical software techniques for improving performance without compromising correctness.

Ideal For

• Hardware verification engineers

• Multicore software engineers

• CPU and cache architecture engineers

• Engineers working with coherent interconnects

• Engineers interested in memory performance and synchronization

Working knowledge of RISC-V ISA concepts, basic UVM and C programming is required.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Three live demonstrations:

  • Proving with SVA in JasperGold that no two caches hold a Modified copy of the same cache line while a UVM scoreboard tracks every write

  • Replaying the saved BOOM Bug B1 test on a Chipyard-built simulator and inspecting TileLink probe timing

  • Removing false sharing using cache-line padding, measuring performance with PMU counters and verifying SPSC queue fence placement with HERD7

• Practical cache-coherency and software-performance analysis

• Ten-minute break and five-minute quiz at the midpoint

This session is Session 3 of the six-session Multicore Programming: Development and Verification Programme.