Multicore Programming | Session 4: SoC Integration and Multicore Software

Multicore Programming | Session 4: SoC Integration and Multicore Software

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Where do multicore bugs hide once processors, interconnects, DMA and power domains are integrated, and how do you verify the software running on the complete system?

This session explores SoC-level integration and multicore software, covering AXI, TileLink and CHI interconnects, PLIC, CLINT, DMA coherency, clock-domain crossing (CDC) and power-gating verification.

You will also examine bare-metal symmetric multiprocessing (SMP) bring-up, CLINT MSIP and inter-processor interrupts (IPIs), data races, AMO and LR/SC primitives, and a verification pyramid spanning unit tests, ThreadSanitizer, CBMC and SPIN.

This session is part of a six-session professional training programme:

• Session 1 — Multi-Hart Verification and RVWMO

• Session 2 — HARTBREAKER and the Confirmed Bugs

• Session 3 — Caches, Coherency and Cache-Aware Software

• Session 4 — SoC Integration and Multicore Software

• Session 5 — Virtual Memory and Hypervisors

• Session 6 — Application-Domain SoCs and Sign-Off

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• AXI, TileLink and CHI interconnects

• PLIC and CLINT functionality

• DMA coherency

• CDC and power-gating verification

• Full-SoC verification tests

• Bare-metal SMP bring-up

• CLINT MSIP and inter-processor interrupts

• Data races in multicore software

• AMO and LR/SC synchronization primitives

• Software verification using ThreadSanitizer, CBMC and SPIN

• Formal investigation of missing memory fences

Why This Matters

Integration introduces interactions between processors, interconnects, interrupts, DMA and power domains that may not be visible in isolated component tests.

This session demonstrates how to investigate integration-level failures and verify multicore software using a combination of hardware analysis, testing and formal techniques.

Ideal For

• SoC verification engineers

• Multicore software engineers

• Hardware and software integration engineers

• RISC-V engineers working with interrupts and shared memory

• Engineers interested in data-race detection and memory-ordering verification

Working knowledge of RISC-V ISA concepts, basic UVM and C programming is required.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Three live demonstrations:

  • Detecting the NaxRiscv CLINT sub-word store violation (N2) at the interconnect level

  • Bringing up bare-metal SMP by releasing secondary harts from hart 0 through CLINT MSIP behind a FENCE W,W

  • Finding a missing fence with Dartagnan that 100,000 test runs miss, and detecting a data race with ThreadSanitizer

• Practical SoC integration and multicore software analysis

• Ten-minute break and five-minute quiz at the midpoint

This session is Session 4 of the six-session Multicore Programming: Development and Verification Programme.