Multicore Programming | Session 5: Virtual Memory and Hypervisors

Multicore Programming | Session 5: Virtual Memory and Hypervisors

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How do page tables, translation lookaside buffers (TLBs) and two-stage address translation give each guest an isolated machine, and how do you verify that these mechanisms work correctly?

This session explores RISC-V virtual memory and hypervisor architecture, covering Sv39 page tables, superpages, TLB architectures with address-space identifiers (ASIDs), Physical Memory Protection (PMP) and six page-fault types.

You will also examine two-stage Sv39x4 translation, VMID and ASID tagging, real TLB bugs in CVA6, NaxRiscv, Rocket and BOOM, the RISC-V H-extension, virtual-machine entry and exit, virtio, VM isolation, IOMMU, hypervisor testing and live migration.

This session is part of a six-session professional training programme:

• Session 1 — Multi-Hart Verification and RVWMO

• Session 2 — HARTBREAKER and the Confirmed Bugs

• Session 3 — Caches, Coherency and Cache-Aware Software

• Session 4 — SoC Integration and Multicore Software

• Session 5 — Virtual Memory and Hypervisors

• Session 6 — Application-Domain SoCs and Sign-Off

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• Sv39 page tables and superpages

• TLB architectures and ASIDs

• Physical Memory Protection (PMP)

• The six page-fault types

• Two-stage Sv39x4 translation

• VMID and ASID tagging

• TLB verification and real CPU TLB bugs

• The RISC-V H-extension

• VM entry and exit

• virtio and VM isolation

• IOMMU and hypervisor testing

• Live migration concepts

Why This Matters

Virtual memory and hypervisors provide address translation and isolation between software environments. Defects in page tables, TLBs or translation mechanisms can compromise correctness and isolation.

This session connects architectural understanding with formal verification and practical observation of a running virtual machine.

Ideal For

• CPU verification engineers

• RISC-V hardware engineers

• Virtualization and hypervisor engineers

• SoC verification engineers

• Engineers working with virtual memory and address translation

Working knowledge of RISC-V ISA concepts, basic UVM and C programming is required.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Three live demonstrations:

  • Walking through an Sv39 translation and classifying the six page-fault types

  • Proving the CVA6 TLB module using SVA properties for one-hot hits, PPN correctness and flush completeness in JasperGold

  • Running a real Linux guest under KVM/RISC-V on QEMU and observing VM entry and exit

• Practical virtual-memory and hypervisor analysis

• Ten-minute break and five-minute quiz at the midpoint

This session is Session 5 of the six-session Multicore Programming: Development and Verification Programme.