Multicore Programming | Session 6: Application-Domain SoCs and Sign-Off

Multicore Programming | Session 6: Application-Domain SoCs and Sign-Off

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What does sign-off mean for automotive, cloud, AI and heterogeneous SoCs, and how do the different verification layers work together to establish system-level confidence?

This session explores domain-specific verification requirements, including automotive ASIL-D, cloud ECC, AI numerical precision and heterogeneous quality of service (QoS).

You will examine post-silicon bring-up, the five-pillar sign-off matrix and domain-specific software environments, including FreeRTOS, Zephyr, Linux SMP with KCSAN and KASAN, ONNX Runtime with RVV and TVM, and OpenAMP/RPMSG.

The session brings together the programme's hardware and software verification methods into a complete block-to-full-stack verification strategy.

This session is part of a six-session professional training programme:

• Session 1 — Multi-Hart Verification and RVWMO

• Session 2 — HARTBREAKER and the Confirmed Bugs

• Session 3 — Caches, Coherency and Cache-Aware Software

• Session 4 — SoC Integration and Multicore Software

• Session 5 — Virtual Memory and Hypervisors

• Session 6 — Application-Domain SoCs and Sign-Off

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• Domain-specific verification for automotive, cloud, AI and heterogeneous SoCs

• Automotive ASIL-D verification requirements

• Cloud error-correcting code (ECC)

• AI numerical precision

• Heterogeneous QoS

• Post-silicon bring-up

• The five-pillar sign-off matrix

• FreeRTOS and Zephyr

• Linux SMP with KCSAN and KASAN

• ONNX Runtime with RVV and TVM

• OpenAMP/RPMSG

• End-to-end hardware and software verification

Why This Matters

A successful component-level verification result does not, by itself, establish that an entire SoC is ready for sign-off.

System-level confidence requires evidence across hardware correctness, software behaviour, performance and application-specific requirements. This session demonstrates how verification methods can be combined into a full-stack sign-off strategy.

Ideal For

• SoC verification engineers

• Hardware and software verification engineers

• Embedded systems engineers

• Engineers working with automotive, cloud or AI hardware

• Engineers involved in heterogeneous SoC integration and sign-off

Working knowledge of RISC-V ISA concepts, basic UVM and C programming is required.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Three live demonstrations:

  • Exhaustively proving SECDED correctness across all 72 single-bit error positions

  • Formally proving FP16 precision and checking ResNet-50 INT8 Top-1 accuracy against the FP32 reference

  • Running a heterogeneous exchange over OpenAMP/RPMSG through FENCE-protected shared-memory ring buffers on verified hardware

• Full-stack sign-off matrix review

• Practical application-domain verification

• Ten-minute break and five-minute quiz at the midpoint

This session is Session 6 and the final session of the six-session Multicore Programming: Development and Verification Programme.