[6 sessions] Multi-Level Hardware Debug: RTL Block to CPU to SoC

[6 sessions] Multi-Level Hardware Debug: RTL Block to CPU to SoC

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This six-session professional training programme covers hardware debugging at three levels: the individual RTL block, the complete CPU, and the full SoC, including its hardware and software.

The programme applies one continuous debugging discipline across all three levels, using the DARE loop (Detect, Analyse, Reproduce, Eliminate) and the halt, inspect and resume model. The sessions combine concise teaching with live demonstrations using buggy RTL, compiled RISC-V binaries and captured GDB and OpenOCD sessions.

The programme consists of six sessions:

• Session 1 — Block-Level Debug: Simulation

• Session 2 — Block-Level Debug: Regression and Formal

• Session 3 — CPU Debug: Toolchain and Debug Module

• Session 4 — CPU Debug: Single-Core, Multi-Core and OS-Aware

• Session 5 — SoC Debug: Hardware Bring-Up and the HW/SW Bridge

• Session 6 — SoC Debug: Fabric, Field Returns and Capstone

What You Will Learn

By the end of this programme, you will:

• Apply the DARE debugging loop to failing RTL and verification results

• Triage UVM logs, trace waveforms and diagnose assertion failures

• Investigate regression failures, minimise failing tests and classify formal counterexamples

• Understand RISC-V debugging through GDB, OpenOCD, JTAG and the Debug Module

• Compare CPU execution against Spike as a golden model

• Diagnose CPU faults, stack errors and multi-core race conditions

• Investigate SoC bring-up failures, JTAG connectivity, secure boot and DMA corruption

• Analyse interconnect congestion, arbitration and multi-hart debug issues

• Apply debugging techniques across hardware, software and their interactions

Why This Matters

Debugging a hardware design requires different tools and techniques depending on whether the failure originates in an RTL block, CPU execution or the complete SoC.

This programme develops one repeatable debugging discipline that can be applied across all three levels, from a failing UVM error message to CPU-level investigation and full SoC bring-up.

Ideal For

• Design verification engineers

• RTL design engineers

• Embedded software engineers

• Engineers working with CPU and SoC verification

• Engineers who want to develop systematic hardware debugging skills

Working knowledge of SystemVerilog, basic UVM and RISC-V assembly is required.

Training Format

• 6 sessions

• 3 hours per session

• 18 hours in total

• Live online training

• 22 live demonstrations across the programme

• Practical exercises using real RTL, compiled RISC-V binaries and debugging tools

• A ten-minute break and five-minute quiz at the midpoint of each session

• Course materials for all six sessions

• Quiz discussion in every session

Tools Covered

VCS, Xcelium, Verdi, VC Formal, Spike, QEMU, GDB and OpenOCD.

Participants need a laptop and a stable internet connection.