Multi-Level Hardware Debug | Session 1: Block-Level Debug — Simulation

Multi-Level Hardware Debug | Session 1: Block-Level Debug — Simulation

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How do you move from a raw UVM_ERROR message to the root cause of a failure in an individual RTL block?

This session introduces systematic simulation debugging, covering the verification flow, UVM testbench structure, bug classification, log triage and waveform tracing. You will apply the DARE loop (Detect, Analyse, Reproduce, Eliminate) to practical RTL failures, investigate X-propagation and debug SVA assertions, deadlocks and livelocks.

The live demonstrations use a buggy ALU, a valid/ready pipeline, and a write-back multiplexer to show how to identify, reproduce, and eliminate common RTL bugs.

This session is part of a six-session professional training programme:

• Session 1 — Block-Level Debug: Simulation

• Session 2 — Block-Level Debug: Regression and Formal

• Session 3 — CPU Debug: Toolchain and Debug Module

• Session 4 — CPU Debug: Single-Core, Multi-Core and OS-Aware

• Session 5 — SoC Debug: Hardware Bring-Up and the HW/SW Bridge

• Session 6 — SoC Debug: Fabric, Field Returns and Capstone

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• The verification flow and UVM testbench anatomy

• The five-category bug taxonomy and S1–S4 severity classification

• The DARE loop: Detect, Analyse, Reproduce and Eliminate

• UVM log triage

• Waveform tracing using Verdi, GTKWave and SimVision

• X-propagation and stale or unknown outputs

• SVA assertion debugging

• Deadlock and livelock diagnosis

• Valid/ready handshake timing and pipeline faults

Why This Matters

A failing simulation may expose a symptom without immediately revealing its root cause. A structured debugging process helps engineers move from an error message to a reproducible failure and a verified correction.

This session demonstrates that process through practical RTL examples and waveform-based investigation.

Ideal For

• Design verification engineers

• RTL design engineers

• Engineers working with UVM testbenches

• Engineers who want to improve their simulation-debugging skills

Working knowledge of SystemVerilog, basic UVM and RISC-V assembly is required for the programme.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Four live demonstrations:

  • Applying the DARE loop to a buggy ALU

  • Tracing a valid-before-data fault in a valid/ready pipeline

  • Locating a handshake timing violation using a concurrent SVA property

  • Fixing a missing-default write-back mux that produces stale or X outputs

• Waveform and log analysis

• Ten-minute break and five-minute quiz at the midpoint

This session is Session 1 of the six-session Multi-Level Hardware Debug Programme.