Multi-Level Hardware Debug | Session 2: Block-Level Debug — Regression and Formal
Multi-Level Hardware Debug | Session 2: Block-Level Debug — Regression and Formal
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Multi-Level Hardware Debug | Session 2: Block-Level Debug — Regression and Formal
We offer a 50% discount to students; please complete this form to avail the discount.
How do you triage a regression failure, and when can you trust a formal counterexample before changing the RTL?
This session focuses on coverage-driven debugging, regression triage and formal counterexample analysis. You will explore how to capture and replay failures, minimise failing tests, classify counterexamples and debug assumptions and guarantees.
The session also compares open-source and commercial EDA tool workflows and examines AI-assisted debugging.
The live demonstrations investigate an FSM stuck in WAIT_ACK, analyse a FIFO control bug using formal verification and compare debugging approaches across different tool environments.
This session is part of a six-session professional training programme:
REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.
What You Will Learn
Coverage-driven debugging and regression triage
The Capture, Replay, Minimise and Bucket workflow
Formal verification concepts and counterexample analysis
Classification of real, spurious and vacuous counterexamples
Assumption and guarantee constraint debugging
Reachability analysis
Open-source and commercial EDA tool workflows
AI-assisted debugging comparisons
Why This Matters
Regression failures can be difficult to reproduce and may originate from different causes. Formal counterexamples also require careful analysis before an engineer can determine whether they expose a genuine design defect.
This session develops practical techniques for reducing failing tests, interpreting formal results and identifying the next debugging action.
Ideal For
Design verification engineers
RTL design engineers
Engineers responsible for simulation regressions
Engineers using formal verification
Engineers interested in improving debugging efficiency
Working knowledge of SystemVerilog, basic UVM and RISC-V assembly is required for the programme.
Training Format
3-hour live online training session
Concise teaching blocks
- Three live demonstrations:
Diagnosing an FSM stuck in WAIT_ACK and creating a directed test through seed capture and minimisation
Classifying and tracing a formal counterexample on a FIFO control bug, then adding an assumption to eliminate a spurious result
Comparing open-source and commercial tool workflows with AI-assisted debugging
Practical regression and counterexample analysis
Ten-minute break and five-minute quiz at the midpoint
This session is Session 2 of the six-session Multi-Level Hardware Debug Programme.