Multi-Level Hardware Debug | Session 3: CPU Debug — Toolchain and Debug Module

Multi-Level Hardware Debug | Session 3: CPU Debug — Toolchain and Debug Module

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What happens inside the hardware when GDB sets a breakpoint, and how does that request reach the CPU core?

This session explores the relationship between software debugging tools and the underlying hardware debug mechanisms. You will examine the halt, read/write and resume primitives, JTAG TAP fundamentals, software and hardware breakpoints, the GDB Remote Serial Protocol, OpenOCD and the RISC-V Debug Module.

The live demonstrations progress from compiling and inspecting a RISC-V program to software debugging in QEMU, hardware debugging through JTAG and OpenOCD, and tracing a GDB register read down to its Abstract Command and DMI transaction.

This session is part of a six-session professional training programme:

• Session 1 — Block-Level Debug: Simulation

• Session 2 — Block-Level Debug: Regression and Formal

• Session 3 — CPU Debug: Toolchain and Debug Module

• Session 4 — CPU Debug: Single-Core, Multi-Core and OS-Aware

• Session 5 — SoC Debug: Hardware Bring-Up and the HW/SW Bridge

• Session 6 — SoC Debug: Fabric, Field Returns and Capstone

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• The halt, read/write and resume primitives of hardware and software debugging

• JTAG TAP fundamentals

• Software versus hardware breakpoints

• The GDB Remote Serial Protocol

• OpenOCD and its role in hardware debugging

• Debug Module internals

• Abstract Commands and the Program Buffer

• System Bus Access

• The Sdtrig Trigger Module

• The relationship between GDB requests and hardware debug transactions

Why This Matters

CPU debugging requires an understanding of how software-level commands interact with the processor's hardware debug infrastructure.

This session connects the debugging workflow used by software engineers with the underlying JTAG, OpenOCD and Debug Module mechanisms.

Ideal For

• CPU verification engineers

• RTL design engineers working with RISC-V processors

• Embedded software engineers

• Engineers working with JTAG, GDB and OpenOCD

• Engineers interested in hardware/software debugging

Working knowledge of SystemVerilog, basic UVM and RISC-V assembly is required.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Four live demonstrations:

  • Compiling a C test using riscv64-unknown-elf-gcc, inspecting it with objdump and loading it into RTL CPU simulation

  • Software debugging using QEMU and GDB

  • Repeating the GDB workflow on real silicon through JTAG and OpenOCD

  • Tracing a GDB register read to its Abstract Command and DMI transaction

• Practical investigation of the CPU debug path

• Ten-minute break and five-minute quiz at the midpoint

This session is Session 3 of the six-session Multi-Level Hardware Debug Programme.