Multi-Level Hardware Debug | Session 4: CPU Debug — Single-Core, Multi-Core and OS-Aware

Multi-Level Hardware Debug | Session 4: CPU Debug — Single-Core, Multi-Core and OS-Aware

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How do you debug a CPU when the problem lies in the RTL, the software or the interaction between multiple HARTs?

This session explores CPU-level debugging, covering comparison against the Spike golden model, register and memory inspection, stack overflows, hard faults and the mcause table. You will also examine reverse debugging with rr, KGDB, multi-core halt groups, Helgrind, ThreadSanitizer and OS-aware debugging with FreeRTOS and Zephyr.

The live demonstrations investigate an architectural mismatch between an RTL CPU and Spike, debug a loop using GDB with Spike as the target, diagnose a stack-pointer fault and track down a shared-counter race between two HARTs.

This session is part of a six-session professional training programme:

• Session 1 — Block-Level Debug: Simulation

• Session 2 — Block-Level Debug: Regression and Formal

• Session 3 — CPU Debug: Toolchain and Debug Module

• Session 4 — CPU Debug: Single-Core, Multi-Core and OS-Aware

• Session 5 — SoC Debug: Hardware Bring-Up and the HW/SW Bridge

• Session 6 — SoC Debug: Fabric, Field Returns and Capstone

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• Comparing an RTL CPU against Spike as a golden model

• Register and memory inspection

• Stack overflows and hard faults

• The mcause table and exception diagnosis

• Reverse debugging with rr

• Kernel debugging using KGDB

• Multi-core halt groups

• Shared-memory race conditions

• Helgrind and ThreadSanitizer

• OS-aware debugging with FreeRTOS and Zephyr

• Investigating watchdog resets

Why This Matters

CPU-level failures can originate from architectural mismatches, software execution, memory corruption or interactions between multiple HARTs.

This session builds practical debugging skills to identify the first point of divergence, examine processor state, and investigate concurrency-related failures.

Ideal For

• CPU verification engineers

• RTL design engineers working with RISC-V processors

• Embedded software engineers

• Engineers working with multi-core systems

• Engineers debugging FreeRTOS or Zephyr applications

Working knowledge of SystemVerilog, basic UVM and RISC-V assembly is required.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Four live demonstrations:

  • Finding the first architectural mismatch between an RTL CPU and Spike

  • Debugging a loop in GDB with Spike as the target

  • Diagnosing a stack-pointer fault (mcause=0x7) from a captured boot.S session

  • Investigating a two-HART shared-counter race using halt groups and hardware watchpoints

• Practical register, memory and execution-state investigation

• Ten-minute break and five-minute quiz at the midpoint

This session is Session 4 of the six-session Multi-Level Hardware Debug Programme.