Multi-Level Hardware Debug | Session 5: SoC Debug — Hardware Bring-Up and the HW/SW Bridge

Multi-Level Hardware Debug | Session 5: SoC Debug — Hardware Bring-Up and the HW/SW Bridge

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When a chip produces no output, how do you debug the hardware before a software debug agent is available?

This session explores the SoC debug path from USB through JTAG and Debug Access Ports (DAPs) to the Debug Module. You will examine boundary scan, trace and logic analysers, post-silicon bring-up, clock-domain crossing (CDC) and power-domain bug classes, lifecycle and secure-boot stages, the seven-layer hardware/software debugging stack, run control, watchpoints and DMA debugging.

The live demonstrations investigate a dead JTAG chain caused by an incorrect TAP order, a Debug Module held in reset, a secure-boot failure identified through OpenTitan lifecycle state and intermittent DMA corruption caused by premature descriptor reuse.

This session is part of a six-session professional training programme:

• Session 1 — Block-Level Debug: Simulation

• Session 2 — Block-Level Debug: Regression and Formal

• Session 3 — CPU Debug: Toolchain and Debug Module

• Session 4 — CPU Debug: Single-Core, Multi-Core and OS-Aware

• Session 5 — SoC Debug: Hardware Bring-Up and the HW/SW Bridge

• Session 6 — SoC Debug: Fabric, Field Returns and Capstone

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• The SoC debug path through USB, JTAG, DAPs and the Debug Module

• Boundary scan

• Trace and logic analysers

• The post-silicon bring-up checklist

• CDC and power-domain bug classes

• Lifecycle states and secure-boot stages

• The seven-layer HW/SW debugging stack

• Run control and hardware watchpoints

• DMA debugging

• Investigating hardware failures before software debugging is available

Why This Matters

SoC bring-up can be difficult when failures occur before normal software debugging becomes available. Engineers need to understand the hardware debug path and systematically investigate connectivity, reset, lifecycle and data-transfer problems.

This session demonstrates how to identify and isolate failures across the SoC's hardware and hardware/software interfaces.

Ideal For

• SoC verification engineers

• RTL design engineers

• Embedded software engineers

• Engineers involved in post-silicon bring-up

• Engineers working with JTAG, secure boot and DMA

Working knowledge of SystemVerilog, basic UVM and RISC-V assembly is required.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Four live demonstrations:

  • Debugging a dead JTAG chain caused by an incorrect TAP order and a Debug Module held in reset

  • Reading OpenTitan lifecycle state to diagnose a secure-boot failure

  • Tracing intermittent DMA corruption to a descriptor reused too early

  • Practical investigation of the SoC bring-up and HW/SW debug path

• Practical hardware bring-up investigation

• Ten-minute break and five-minute quiz at the midpoint

This session is Session 5 of the six-session Multi-Level Hardware Debug Programme.