Multi-Level Hardware Debug | Session 6: SoC Debug — Fabric, Field Returns and Capstone

Multi-Level Hardware Debug | Session 6: SoC Debug — Fabric, Field Returns and Capstone

We offer a 50% discount to students; please complete this form to avail the discount.

How does one debugging discipline carry from a single RTL signal to a complete SoC bring-up?

This final session explores interconnect congestion and arbitration, multi-HART debug fabrics, interrupt and exception handling, multi-core halt groups, SMP versus AMP and application debugging across bare-metal, RTOS and Linux environments.

You will also examine postmortem field-return analysis, optional lockstep checking and the complete end-to-end debugging workflow.

The live demonstrations investigate an interconnect congestion timeout on the PULP AXI crossbar, identify a HART that is never granted access in a multi-HART debug fabric, analyse a field return using logs alone and conclude with an end-to-end debugging capstone.

This session is part of a six-session professional training programme:

• Session 1 — Block-Level Debug: Simulation

• Session 2 — Block-Level Debug: Regression and Formal

• Session 3 — CPU Debug: Toolchain and Debug Module

• Session 4 — CPU Debug: Single-Core, Multi-Core and OS-Aware

• Session 5 — SoC Debug: Hardware Bring-Up and the HW/SW Bridge

• Session 6 — SoC Debug: Fabric, Field Returns and Capstone

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• Interconnect congestion and arbitration

• Multi-HART debug fabrics

• Interrupt and exception handling using mcause, mepc and mtval

• Multi-core halt groups

• Symmetric multiprocessing (SMP) versus asymmetric multiprocessing (AMP)

• Debugging bare-metal, RTOS and Linux applications

• Postmortem field-return analysis

• Optional lockstep checking

• End-to-end hardware and software debugging

Why This Matters

SoC-level failures can involve multiple HARTs, interconnects, interrupts, software and hardware interactions. Effective debugging requires engineers to connect evidence from different parts of the system rather than investigate each component in isolation.

This session brings the programme's debugging methods together, demonstrating how the same discipline can be applied to interconnect failures, starvation, field returns and full-system bring-up.

Ideal For

• SoC verification engineers

• CPU and RTL design engineers

• Embedded software engineers

• Engineers working with multi-core systems

• Engineers involved in SoC bring-up and field-failure investigation

Working knowledge of SystemVerilog, basic UVM and RISC-V assembly is required.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Four live demonstrations:

  • Diagnosing an interconnect congestion timeout on the PULP AXI crossbar using a VC Formal fairness property

  • Finding a HART that is never granted access through a formal starvation counterexample

  • Diagnosing a field return using logs alone

  • Completing the end-to-end debugging capstone

• Practical application of the debugging methodology across the SoC

• Ten-minute break and five-minute quiz at the midpoint

This session is Session 6 and the final session of the Multi-Level Hardware Debug Programme.