[6 sessions] Full-Stack Low-Power Verification

[6 sessions] Full-Stack Low-Power Verification

We offer a 50% discount to students; please complete this form to avail the discount.

This is a six-session professional training programme covering low-power verification across three levels: power-aware RTL and UPF at block level, DVFS, idle and wakeup at CPU level, and PMU, sleep/wake and OS power management at SoC level.

The programme combines hardware and software perspectives throughout, connecting power-management concepts on the RTL/UPF side with firmware and software behaviour.

The sessions combine concise teaching with live demonstrations on OpenTitan and Ibex, using VCS, Xcelium and JasperGold LP, with CVA6, OpenSBI and U-Boot for firmware co-simulation.

The programme consists of six sessions:

• Session 1 — Low-Power Foundations and Block-Level Gating

• Session 2 — Power FSMs, UPF Simulation and Block Sign-Off

• Session 3 — DVFS, Idle and Cluster Power Management

• Session 4 — Constrained-Random, Formal and Boot Power

• Session 5 — SoC Power Architecture, Suspend and Resume

• Session 6 — OS Power Management and the Full Stack

What You Will Learn

By the end of this programme, you will:

• Understand power domains, supply nets and UPF intent

• Verify clock gating, power gating, isolation and retention

• Develop power-aware UVM testbenches and use SVA and formal verification

• Verify power state machines, reset sequencing and power-state coverage

• Understand dynamic voltage and frequency scaling (DVFS), CPU idle and wakeup

• Investigate CPU-level power behaviour and firmware co-simulation

• Verify boot power sequencing, deep sleep, wakeup and power-on reset behaviour

• Understand SoC power architecture, PMU RTL and firmware

• Verify suspend-to-RAM, resume and wakeup sequencing

• Explore Linux power-management drivers, Runtime PM and cpufreq governors

• Connect UPF intent, RTL verification, firmware behaviour and OS power policy

• Prepare a full-stack low-power verification sign-off report

Why This Matters

Power-management correctness requires more than functional RTL verification. A design must behave correctly across power states, clock and power transitions, CPU idle and wakeup, SoC suspend/resume, and operating-system power-management decisions.

This programme develops a practical verification methodology that follows power behaviour from block-level RTL and UPF through CPU and SoC integration to firmware and OS power policy.

Ideal For

• Verification engineers moving to power-aware verification

• Design engineers working with low-power hardware

• Firmware engineers who want to understand the hardware their power-management code drives

Working knowledge of UVM and SystemVerilog and basic digital design is required. No prior UPF experience is needed.

Training Format

• 6 sessions

• 3 hours per session

• 18 hours in total

• Live online training

• 10 live demonstrations across the programme

• Demonstrations on real open-source designs and tools

• A ten-minute break and five-minute quiz at the midpoint of every session

• Course materials for all six sessions

• Quiz discussion in every session

Tools and Technologies Covered

UPF, power-aware UVM, SVA, VCS, Xcelium, JasperGold LP, OpenTitan, Ibex, CVA6, OpenSBI, U-Boot, RISC-V-DV and Spike.

Participants need a laptop and a stable internet connection.