Full-Stack Low-Power Verification | Session 1: Low-Power Foundations and Block-Level Gating

Full-Stack Low-Power Verification | Session 1: Low-Power Foundations and Block-Level Gating

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What does it mean for a hardware block to be correct in every power state, not just functionally?

This session introduces power-aware verification at block level, covering power domains, supply nets, UPF intent and why a standard UVM testbench cannot catch every power-domain bug.

You will explore clock gating from the ICG cell to UPF, power gating using switches, isolation and sequencing, and retention flops using set_retention and the retention controller.

The live demonstrations verify the OpenTitan clock manager at block level in UVM on VCS and Xcelium, with JasperGold formal results, then investigate the power manager's fast and slow FSMs through aborted low-power, wakeup-race and repeat-wakeup-reset tests.

This session is part of a six-session professional training programme:

• Session 1 — Low-Power Foundations and Block-Level Gating

• Session 2 — Power FSMs, UPF Simulation and Block Sign-Off

• Session 3 — DVFS, Idle and Cluster Power Management

• Session 4 — Constrained-Random, Formal and Boot Power

• Session 5 — SoC Power Architecture, Suspend and Resume

• Session 6 — OS Power Management and the Full Stack

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• Power domains, supply nets and UPF intent

• Why standard UVM testing alone cannot catch power-domain bugs

• Clock gating from ICG cells to UPF

• Power gating using switches

• Isolation and power sequencing

• Retention flops and set_retention

• Retention controller behaviour

• Block-level verification of clock and power managers

• Fast and slow power-manager FSMs

• Aborted low-power, wakeup-race and repeat-wakeup-reset scenarios

Why This Matters

A block may function correctly during normal operation but fail when clocks or power domains are switched. Verification must therefore account for power-state transitions, isolation, retention and wakeup behaviour.

This session establishes the foundations for verifying low-power hardware at block level using power-aware simulation and formal evidence.

Ideal For

• Verification engineers moving to power-aware verification

• RTL design engineers working with clock and power management

• Design engineers interested in UPF-based verification

Working knowledge of UVM and SystemVerilog and basic digital design is required. No prior UPF experience is needed.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Live demonstrations:

  • Verifying the OpenTitan clock manager using UVM on VCS and Xcelium, with JasperGold formal results, covering peripheral and transactional clock gating through smoke, peri and trans tests

  • Verifying the power manager's fast and slow FSMs through aborted low-power, wakeup-race and repeat-wakeup-reset tests

• A ten-minute break and five-minute quiz at the midpoint

• Practical analysis of block-level low-power verification

This session is Session 1 of the six-session Full-Stack Low-Power Verification Programme.