Full-Stack Low-Power Verification | Session 2: Power FSMs, UPF Simulation and Block Sign-Off

Full-Stack Low-Power Verification | Session 2: Power FSMs, UPF Simulation and Block Sign-Off

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How do you turn power intent into verification evidence and document the results in a block-level sign-off report?

This session explores power state machines, safe reset sequencing, UPF power-state tables and corruption modes in VCS and Xcelium.

You will also cover power-aware coverage, SVA, side-channel power analysis, masking countermeasures and the structure of a block-level low-power verification report.

The live demonstrations verify the OpenTitan reset manager at block level in UVM on VCS and Xcelium, with JasperGold formal results and coverage. Smoke, reset and POR-stretcher tests cover power-on and warm-reset paths and the reset manager's interaction with the power manager. The session concludes with the report.

This session is part of a six-session professional training programme:

• Session 1 — Low-Power Foundations and Block-Level Gating

• Session 2 — Power FSMs, UPF Simulation and Block Sign-Off

• Session 3 — DVFS, Idle and Cluster Power Management

• Session 4 — Constrained-Random, Formal and Boot Power

• Session 5 — SoC Power Architecture, Suspend and Resume

• Session 6 — OS Power Management and the Full Stack

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• Power state machines and safe reset sequencing

• UPF power-state tables

• Corruption modes in VCS and Xcelium

• Power-aware coverage and SVA

• Side-channel power analysis

• Masking countermeasures

• Block-level low-power verification reporting

• Reset-manager verification using simulation and formal results

• Power-on and warm-reset paths

• Interaction between the reset manager and power manager

Why This Matters

Power intent must be translated into observable verification evidence. Power-state behaviour, reset sequencing and corruption modes need to be checked, and the results must be documented clearly enough to support block-level sign-off.

This session connects power-aware simulation and formal verification to preparing a low-power verification report.

Ideal For

• Verification engineers working with low-power designs

• RTL engineers responsible for reset and power-management logic

• Engineers preparing block-level verification sign-off reports

Working knowledge of UVM and SystemVerilog and basic digital design is required. No prior UPF experience is needed.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Live demonstration:

  • Verifying the OpenTitan reset manager in UVM on VCS and Xcelium, using JasperGold formal results and coverage, with smoke, reset and POR-stretcher tests covering power-on and warm-reset paths and interaction with the power manager

• Preparation of the block-level low-power verification report

• A ten-minute break and five-minute quiz at the midpoint

This session is Session 2 of the six-session Full-Stack Low-Power Verification Programme.