Full-Stack Low-Power Verification | Session 3: DVFS, Idle and Cluster Power Management

Full-Stack Low-Power Verification | Session 3: DVFS, Idle and Cluster Power Management

We offer a 50% discount to students; please complete this form to avail the discount.

How does a CPU cluster change voltage, frequency and power state without breaking the firmware that controls it?

This session explores dynamic voltage and frequency scaling (DVFS), including operating performance points (OPPs), PLL and clock management, wide-datapath power, CPU idle and WFI.

You will also cover hotplug, per-core power domains, the power domain manager, the wakeup controller and the firmware that drives these components.

The live demonstrations verify the dvfs_controller on Xcelium against its power profiles and operating points, including the safe-transition property and a hysteresis bug that standard verification misses. You will then follow Ibex through a sleep and wake cycle to measure the cost of clock gating and clock-gate release timing.

This session is part of a six-session professional training programme:

• Session 1 — Low-Power Foundations and Block-Level Gating

• Session 2 — Power FSMs, UPF Simulation and Block Sign-Off

• Session 3 — DVFS, Idle and Cluster Power Management

• Session 4 — Constrained-Random, Formal and Boot Power

• Session 5 — SoC Power Architecture, Suspend and Resume

• Session 6 — OS Power Management and the Full Stack

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• DVFS architecture and operating performance points

• PLL and clock management

• Wide-datapath power

• CPU idle and WFI

• Hotplug and per-core power domains

• Power domain manager behaviour

• Wakeup controller operation

• Firmware-driven power management

• Safe voltage and frequency transitions

• Clock gating and clock-gate release timing

Why This Matters

CPU power management involves coordinated transitions between voltage, frequency and power states. These transitions must preserve correct CPU behaviour and work with the firmware that manages them.

This session connects DVFS and CPU idle concepts with practical verification of power transitions and wakeup timing.

Ideal For

• CPU verification engineers

• RTL design engineers working with DVFS and clock management

• Firmware engineers working with CPU power management

• Verification engineers moving from block-level to CPU-level power verification

Working knowledge of UVM and SystemVerilog and basic digital design is required. No prior UPF experience is needed.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Live demonstrations:

  • Verifying the dvfs_controller on Xcelium against power profiles and operating points, including the safe-transition property and a hysteresis bug missed by standard verification

  • Following Ibex through a sleep and wake cycle to measure the cost of clock gating and clock-gate release timing

• A ten-minute break and five-minute quiz at the midpoint

• Practical analysis of CPU and cluster power management

This session is Session 3 of the six-session Full-Stack Low-Power Verification Programme.