Full-Stack Low-Power Verification | Session 4: Constrained-Random, Formal and Boot Power

Full-Stack Low-Power Verification | Session 4: Constrained-Random, Formal and Boot Power

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How do you reach power-state coverage closure and prove sequencing properties that simulation can only sample?

This session covers constrained-random, power-aware UVM testbenches; power-state coverage closure; SVA power assertions; and JasperGold LP formal verification.

You will also explore secure and safe boot power sequencing, including bootrom, safe_boot and dram_init, as well as CPU-level power simulation and firmware co-simulation in an instruction-set simulator (ISS) alongside the RTL.

The live demonstrations verify Ibex's WFI low-power behaviour using RISC-V-DV-generated tests compared against Spike, with log-trace comparison on VCS and Xcelium. You will also verify reset-to-first-fetch boot sequencing from cold reset using riscv_arithmetic_basic_test, comparing waveforms and coverage on both simulators.

This session is part of a six-session professional training programme:

• Session 1 — Low-Power Foundations and Block-Level Gating

• Session 2 — Power FSMs, UPF Simulation and Block Sign-Off

• Session 3 — DVFS, Idle and Cluster Power Management

• Session 4 — Constrained-Random, Formal and Boot Power

• Session 5 — SoC Power Architecture, Suspend and Resume

• Session 6 — OS Power Management and the Full Stack

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• Constrained-random power-aware UVM testbenches

• Power-state coverage closure

• SVA power assertions

• JasperGold LP formal verification

• Secure and safe boot power sequencing

• Bootrom, safe_boot and dram_init

• CPU-level power simulation

• Firmware co-simulation alongside RTL

• Ibex WFI low-power behaviour

• Reset-to-first-fetch sequencing from cold reset

• Waveform, log-trace and coverage comparison

Why This Matters

Power-state coverage and boot sequencing require verification evidence beyond a small number of sampled simulation scenarios. Constrained-random testing, assertions and formal verification help investigate power-related behaviours, while firmware co-simulation connects the RTL implementation to software-driven execution.

This session combines these techniques to verify CPU low-power behaviour and boot sequencing.

Ideal For

• CPU verification engineers

• Verification engineers using UVM and formal methods

• RTL engineers working on boot and reset logic

• Firmware engineers interested in hardware/software co-simulation

Working knowledge of UVM and SystemVerilog and basic digital design is required. No prior UPF experience is needed.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Live demonstrations:

  • Verifying Ibex WFI low-power behaviour using OpenTitan, RISC-V-DV-generated tests, Spike comparison and log-trace analysis on VCS and Xcelium, using riscv_interrupt_wfi_test

  • Verifying reset-to-first-fetch boot sequencing from cold reset using riscv_arithmetic_basic_test, comparing waveforms and coverage on both simulators

• A ten-minute break and five-minute quiz at the midpoint

• Practical analysis of power-state coverage and boot sequencing

This session is Session 4 of the six-session Full-Stack Low-Power Verification Programme.