Full-Stack Low-Power Verification | Session 5: SoC Power Architecture, Suspend and Resume

Full-Stack Low-Power Verification | Session 5: SoC Power Architecture, Suspend and Resume

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How does a power management unit (PMU) orchestrate an entire chip into deep sleep and bring it back, and how can you verify every step?

This session explores SoC power architecture and the power-design verification plan, including hardware/software co-verification of the CPU and SoC.

You will examine PMU RTL and firmware components, including pmu_controller, pmu_fsm, pmu_seq and pmu_regs. The session also covers suspend-to-RAM, resume and wakeup sequencing with formal checks of wakeup ordering, alongside thermal management in RTL and firmware.

The live demonstrations verify deep-sleep wakeup on OpenTitan Earl Grey with a software-driven test across every wakeup source. You will then run the chip_sw_pwrmgr_deep_sleep_por_reset test to check the expected reset sequence when power-on reset occurs during deep sleep, using VCS and Xcelium.

This session is part of a six-session professional training programme:

• Session 1 — Low-Power Foundations and Block-Level Gating

• Session 2 — Power FSMs, UPF Simulation and Block Sign-Off

• Session 3 — DVFS, Idle and Cluster Power Management

• Session 4 — Constrained-Random, Formal and Boot Power

• Session 5 — SoC Power Architecture, Suspend and Resume

• Session 6 — OS Power Management and the Full Stack

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• SoC power architecture and the power DV plan

• Hardware/software co-verification of the CPU and SoC

• PMU RTL and firmware

• pmu_controller, pmu_fsm, pmu_seq and pmu_regs

• Suspend-to-RAM and resume

• Wakeup sequencing and formal checks of wakeup ordering

• Deep-sleep wakeup sources

• Power-on reset during deep sleep

• Thermal management in RTL and firmware

Why This Matters

Deep-sleep entry and wakeup involve coordinated actions across the PMU, CPU, SoC hardware and firmware. Reset events during low-power states introduce additional sequencing requirements that must be verified.

This session demonstrates how to verify software-driven wakeup behaviour and confirm the expected reset sequence when power-on reset occurs during deep sleep.

Ideal For

• SoC verification engineers

• RTL engineers working with PMUs and power controllers

• Firmware engineers responsible for suspend and resume

• Engineers working with low-power SoC integration

Working knowledge of UVM and SystemVerilog and basic digital design is required. No prior UPF experience is needed.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Live demonstrations:

  • Verifying deep-sleep wakeup on OpenTitan Earl Grey with a software-driven test covering every wakeup source

  • Running chip_sw_pwrmgr_deep_sleep_por_reset on VCS and Xcelium to check the expected reset sequence when power-on reset occurs during deep sleep

• A ten-minute break and five-minute quiz at the midpoint

• Practical investigation of SoC suspend, resume and wakeup sequencing

This session is Session 5 of the six-session Full-Stack Low-Power Verification Programme.