Full-Stack Low-Power Verification | Session 6: OS Power Management and the Full Stack

Full-Stack Low-Power Verification | Session 6: OS Power Management and the Full Stack

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How can a single power scenario be traced from UPF intent through hardware and firmware to operating-system power policy?

This session explores Linux power-management drivers, including cpufreq, cpuidle, regulator, thermal and power domains. You will also cover device-tree power-domain bindings, Runtime PM, cpufreq governors, suspend and hibernate.

The session examines how operating-system power decisions depend on workload, thermal state and battery status, alongside AI-based DVFS and workload prediction. It concludes with the full-stack low-power verification sign-off report.

The live demonstration verifies a sensor-controller alert wakeup at SoC level on VCS and Xcelium, covering the two paths by which the chip responds to an event and the corner case that requires special handling.

This session is part of a six-session professional training programme:

• Session 1 — Low-Power Foundations and Block-Level Gating

• Session 2 — Power FSMs, UPF Simulation and Block Sign-Off

• Session 3 — DVFS, Idle and Cluster Power Management

• Session 4 — Constrained-Random, Formal and Boot Power

• Session 5 — SoC Power Architecture, Suspend and Resume

• Session 6 — OS Power Management and the Full Stack

REGISTRATION FOR ALL 6 SESSIONS IS 210$ ONLY.

What You Will Learn

• Linux power-management drivers: cpufreq, cpuidle, regulator, thermal and power domains

• Device-tree power-domain bindings

• Runtime PM and cpufreq governors

• Suspend and hibernate

• OS power decisions based on workload, thermal state and battery status

• AI-based DVFS and workload prediction

• Sensor-controller alert wakeup

• Full-stack low-power verification sign-off reporting

• Tracing power behaviour across hardware and software verification layers

Why This Matters

Low-power behaviour extends beyond RTL. Firmware and operating-system policies influence how hardware enters low-power states, responds to events and resumes operation.

This session connects UPF intent, hardware behaviour and OS power policy through a sensor-alert wakeup scenario, bringing together the verification layers used throughout the programme.

Ideal For

• Verification and design engineers working with low-power systems

• Firmware engineers working with power-management code

• Engineers involved in SoC power verification

• Engineers interested in Linux power management and full-stack sign-off

Working knowledge of UVM and SystemVerilog and basic digital design is required. No prior UPF experience is needed.

Training Format

• 3-hour live online training session

• Concise teaching blocks

• Live demonstration:

  • Verifying a sensor-controller alert wakeup at SoC level on VCS and Xcelium, covering both chip-response paths and the corner case requiring special handling

• Full-stack low-power verification sign-off report

• A ten-minute break and five-minute quiz at the midpoint

• Practical tracing of a power scenario across verification layers

This session is Session 6 and the final session of the Full-Stack Low-Power Verification Programme.