Designing the Future : Analogue Mixed Signal
Designing the Future : Analogue Mixed Signal
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Join us as Regent’s University London, Inner Circle, Regent’s Park, London NW1 4NS
Running concurrently at the same venue, TechWorks and UKESF are hosting a Chip Design Early Careers event which will bring together industry and emerging talent. The UKESF Digital Design – Early Careers track, will give companies the opportunity to engage with up to 50 students and graduates: next-generation chip designers at the point where they are actively making career choices. Participants can speak directly to students and early-career engineers who want to learn more about chip design as a career, and which organisations they can join and grow with.
As complexity accelerates, designers face growing challenges in architecture, design, system scaling and workflow.
Following our Digital Design event in November, this next event brings together Analogue and Mixed Signal chip architects and designers to explore real-world pain points and application trends. During the day, we will hear from experts about the challenges and opportunities facing industry and identify how, by working together, we can support industry growth.
The event is structured around three contemporary themes, with a plenary discussion after each to discuss the topics raised and identify relevant actions going forward.
Running concurrently at the same venue, TechWorks and UKESF are hosting a Chip Design Early Careers event to bring together industry and emerging talent. The UKESF Digital Design – Early Careers track, will give companies the opportunity to engage with up to 50 next-generation chip designers (students and graduates) at the point where they are making career choices. Participants can speak directly to these early-career engineers who are keen to learn about a career in chip design, and which organisations they can join and grow with.
Overview
- The future of AMS Design
How is AMS design evolving and where are we compared with pure-play digital CMOS
- Design for performance, noise, and integrity across PVT
- Trade-offs across process nodes and scaling limits; voltage, noise, performance, cost
- Design migration, IP integration and reuse
- Design flow and productivity: How can automation and AI help?
- Layout challenges, routing, optimization and physical verification
- Co-simulation, model abstraction and system-level verification
- System architecture and Integration
Meeting system requirements while avoiding parasitics and interference is not just a circuit-level challenge. What are the current trends in system architecture and integration?
- System partitioning, simulation and integration: Performance / Power / Area
- Digital-analogue interfacing and interconnect. Interference mitigation and isolation
- Multi-die integration: Yield reliability, Power delivery, Thermal management
- Signal integrity and noise coupling in advanced packaging, 2.5D and 3D
- Multi-die mixed signal chiplets and heterogeneous integration
- Application drivers for AMS Design
Many emerging technologies are driving AMS innovation. What are the major application challenges pushing the frontier of analogue design today?
- Future compute and AI
- High-speed SerDes, Photonic interconnect, Clock & data recovery
- Power delivery, voltage regulation and monitoring
- Analog and in-memory compute
- IoT, connectivity, med-tech and wearables
- Low-noise analogue sensor integration / Energy harvesting
- Physical AI / Neuromorphic compute
- Low power RF
AGENDA
| TIME | DETAILS |
|---|---|
| 09:15 | Registration |
| 10:00 | TechWorks DESN Introduction - Scene setting & objectives Jillian Hughes, Head of Semiconductors, DESN & Charles Sturman, CEO, TechWorks |
| The Future of AMS Design How is AMS design evolving and where are we compared with pure-play digital CMOS |
|
| 10:10 | System-First Design for High-Performance Mixed-Signal Asad Ali, Senior IC Architect, Novamorphic |
| 10:30 | Bridging the Verification Gap Between Digital and Analog IC Design Marcel Ahmedzai, Application Engineer Architect, Cadence |
| 10:50 | Top‑Down Approach to Mixed‑Signal Verification Gautham Sathyan, Mixed Signal Modeling & Verification Engineer, Cirrus Logic |
| 11:10 | Verifying AMS Designs Mike Bartley, CEO, Alpinum |
| 11:30 | Discussion and CTA |
| 11:55 | Sponsor talk: Lee Harrison, Director of Product Marketing, Tessent, Siemens EDA |
| 12:00 | Networking Lunch |
| System architecture and Integration Meeting system requirements while avoiding parasitics and interference is not just a circuit-level challenge. What are the current trends in system architecture and integration? |
|
| 13:00 | Structured AMS migration: Device-level validation to layout closure with intelligent automation Chris Yates, Head of AI and Machine Learning, Thalia |
| 13:20 | Revolutionizing Analog Layout Synthesis through GenAI and Machine Learning Technologies Neel Goplan, Executive Director, Technical Product Management |
| 13:40 | Beyond 1.8 V: Enabling Robust 3.3 V Interfaces in 28 nm CMOS and 7 nm FinFET with Overvoltage Tolerant Specialty I/Os Bart Keppens, Chief Business Development, Sofics |
| 14:00 | Discussion & Call to Action |
| 14:25 | Break |
| Application drivers for AMS Design Many emerging technologies are driving AMS innovation. What are the major application challenges pushing the frontier of analogue design today? |
|
| 15:10 | AMS from beamforming arrays to safety critical ASICs Konstantinos Glaros, Associate Director - Analogue IC Design, Ensilica Plc |
| 15:20 | Analog Scan: A new frontier for Mixed-signal test Vladimir Zivkovic, Principal Product Engineer, Siemens EDA |
| 15:40 | Discussion & Call to Action |
| 16:05 | Refreshments and Networking |
| 17:00 | Close |
Location
London, NW1 4NS