Webinar 2: Tessolve AI assisted DV Flow
Webinar 2 :Tessolve AI assisted DV Flow
With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification, Tessolve has been working on improving internal DV processes, with impressive reductions in both effort and costs, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short webinars, Tessolve will outline the work done to demonstrate the potential for improving both productivity and quality, and how you could get involved in this (zero cost) collaboration to capture similar benefits.
Agenda (GMT)
15:00 Welcome and Introduction – Mike Bartley, Tessolve
15:00 Marmik Soni & Mike Bartley, Tessolve Semiconductor
15:20 Close
Additional Information Tessolve AI assisted DV Flow
- Spec Analysis
- Register Extraction
- Test Flow
- Assertion Generation
- Coverpoints
- Testcases
- Scripts for UVM etc.
Tessolve reserves the right to cancel registration at its discretion.