On-Demand recordings access | Part 1: Introduction to CPU and CPU Verification

We offer 50% discount to students, please complete this form to avail discount.

This is a part of a 3-session series:

• Part 1 – Introduction to CPU and CPU Verification - 16-17 April and 20-21 April 2026, 8.30 to 12.00
• Part 2 – RISC-V CPU Verification - 4 - 8 May 2026, 8.30 to 12.00
• Part 3 – RISC-V SoC Verification - 27-29 May and 1 June 2026, 8.30 to 12.00

REGISTRATION FOR ALL 3 SESSIONS IS AT £499 ONLY.

Part 1 introduces the fundamentals of CPU design and verification. Participants will explore CPU architectures and instruction set architectures (ISA), microarchitecture design, and hierarchical verification strategies at the unit, CPU, and system levels. The course covers instruction stream generation and open-source tools such as riscv-dv, as well as functional coverage modeling, test generation, and practical verification exercises. Students will gain hands-on experience through exercises designed to extend coverage models and constraints, with guided classroom review sessions to reinforce learning. This part provides the foundation for understanding CPU verification and prepares participants for more advanced RISC-V and SoC verification topics.

Agenda:

• Introduction to CPU architectures and instruction set architectures (ISA)

• CPU microarchitecture fundamentals

• CPU verification strategies: unit, CPU, and system-level

• Instruction stream generators and riscv-dv overview

• Functional coverage modeling and test generation

• Practical exercises with joint classroom review

Participants may also enrol in the Complete Program, which includes additional advanced modules, Moodle access, quizzes, exams, advanced verification strategies, and extra design examples.