On-Demand recordings access | Part 2: RISC-V CPU Verification | 3-Part RISC-V Verification Course

This is a part of a 3-session series:

• Part 1 – Introduction to CPU and CPU Verification - 16-17 April and 20-21 April 2026, 8.30 to 12.00
• Part 2 – RISC-V CPU Verification - 4 - 8 May 2026, 8.30 to 12.00
• Part 3 – RISC-V SoC Verification - 27-29 May and 1 June 2026, 8.30 to 12.00

REGISTRATION FOR ALL 3 SESSIONS IS AT £499 ONLY.

Part 2 focuses on verifying RISC-V CPUs and building practical experience with RISC-V software and hardware tools. Participants will learn the RISC-V ISA, assembly language, software toolchains, and how to run programs using the RARS simulator. The course includes hands-on exercises with riscv-dv, teaching test generation, functional coverage, and constraint modeling. Architectural compliance and advanced CPU microarchitectures, including pipelining, superscalar, and multithreaded processors, are covered to deepen understanding. Practical exercises and classroom review sessions ensure that participants can confidently verify RISC-V CPUs and contribute effectively to CPU verification projects..

Agenda:

• Overview of RISC-V ISA and assembly language

• Software toolchains for RISC-V

• Writing and running assembler and C programs on RARS

• Using riscv-dv for test generation, constraints, and functional coverage

• Architectural compliance and advanced CPU microarchitectures

• Practical exercises and classroom review

Participants may also enrol in the Complete Program, which includes additional advanced modules, Moodle access, quizzes, exams, advanced verification strategies, and extra design examples.