AI in Design Verification

This session will be recorded and will be available to all registrants post-session.

Artificial Intelligence is reshaping the future of semiconductor design — and Design Verification is at the forefront of this transformation.

From automated UVM generation to intelligent debug and coverage closure, AI is enabling verification teams to move faster, reduce manual effort, and tackle increasing design complexity with greater confidence.

Join us at DV Club Edinburgh as we explore the latest developments in AI-driven verification methodologies, bringing together industry experts to share real-world insights, practical applications, and emerging trends.

This event provides a unique opportunity to learn how AI is being applied in production environments, understand its limitations, and explore how verification teams can safely and effectively adopt these technologies.

Agenda (GMT)

         Time                    Details

         12.00                   Arrival, registration, networking, light refreshments

         13:00                   AI as a Cognitive Amplifier in Modern Design Verification
                                      by Simon Davidmann, Southampton University

         13:30                   AVL: open source UVM verification
                                      by Rafael Frangulyan Polyak, Axelera AI

         14:00                   Open Source Security Silicon -- An AI Perspective
                                      by Colin McKellar, lowRISC

         14:30                   AI in DV: Where It Helps, Where It Hurts, and How to Pilot Safely
                                      by Mike Bartley, Alpinum Consulting

         15:00                   Break with refreshments/networking

         15:30                   Quality Aware Formal Verification
                                      by Ramesh Krishnamurthy, APRIL AI Hub, University of Edinburgh

         16:00                   Agentic Formal Verification At The Example of Floating Point Units (FPUs)
                                      by Moustafa Kishar, Siemens EDA

         16:30                   Cadence AgentStack – Agentic AI for Verification and Beyond
                                      by Matt Graham, Cadence Design Systems

         17:00                   AI in Design Verification : What works, what doesn’t and what comes next
                                      by Andy Montador, Analog Devices

         17:30                   Refreshments/networking   

👉 Also Register for the Design Verification training (morning session)

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