Hands-on AI in Design Verification Training

We offer 50% discount to students, please complete this form to avail discount.

This session will be recorded and will be available to all registrants 1 week post-session.

Format: Hybrid: In-person and online

Overview

AI is rapidly transforming Design Verification (DV) — enabling engineers to automate testbench generation, improve coverage, and significantly reduce debug effort.

This hands-on half-day training provides a practical introduction to how Generative AI, Machine Learning, and intelligent automation can be applied across RTL and verification workflows.

Participants will not only learn key concepts, but also actively work through guided exercises using pre-configured cloud environments, ensuring immediate, real-world application.

Designed as a condensed version of our full-day training, this session delivers high-impact insights alongside practical, interactive experience to help engineers quickly understand where AI can deliver immediate value in DV projects.

⚠️ Important Setup Requirements (Please Read Carefully)

To ensure a smooth hands-on experience:

• You must bring your own laptop
• Mac users may require additional setup time (not preferred)
• All participants will receive login details in advance for a pre-configured AWS environment (with all required tools pre-installed)

👉 Please ensure you have access to your credentials before arrival to maximise hands-on time during the session.

Who Should Attend

• Design Verification engineers using SystemVerilog / UVM
• RTL and SoC engineers exploring AI-driven workflows
• Engineers looking to improve verification productivity
• Technical leads evaluating AI adoption in DV

Learning Objectives

By the end of the session, you will be able to:

• Understand key AI approaches used in verification (GenAI, ML, RL)
• Apply AI to testbench generation and RTL validation
• Identify opportunities for coverage optimisation and debug automation
• Evaluate where AI can accelerate your current DV workflows

Agenda Highlights

AI Fundamentals for DV

• Overview of GenAI, ML, RL and their role in hardware design

AI in RTL & Verification (Hands-On)

• AI-assisted RTL coding and analysis
• Spec-to-UVM generation
• AI-driven testbench creation

Coverage & Debug Automation (Hands-On)

• ML-based coverage prediction
• AI-assisted debug and log analysis

Tools & Practical Adoption

• Open-source vs enterprise tools
• Integration into existing DV flows
• Working within a cloud-based (AWS) DV environment

👉 Also Register Edinburgh DV Club

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