AI Methods in VLSI & DV | Part 1: AI in DV and VLSI

This session will be recorded and will be available to all registrants 1 week post-session.

Consists of the three sessions:

• 11 May 2026 – AI Methods in VLSI & DV
• 18 May 2026 – Benefits, Limitations & Case Studies
• 25 May 2026 – AI Flows, Deployment & Execution

Register for all 3 sessions of the AI in DV and VLSI training series for only $49

This focused three-part series explores how AI is transforming VLSI design and Design Verification (DV) — from code generation to autonomous verification workflows.

Participants will gain a clear understanding of how AI can be applied today, what works in production, and how to safely deploy AI within verification environments.

Session 1 – AI Methods in VLSI & DV

• AI fundamentals: GenAI, ML, RL, Genetic Algorithms

• AI in VLSI design (auto-coding, linting, HLS acceleration)

• AI in DV: testbench generation, coverage optimisation, debug automation