Advanced Properties, Sequences & Auxiliary Logic | Part 2: SystemVerilog Assertions (SVA) for Verification Engineers

This is a part of a 3-session series:

• 18 June 2026 – Foundations & Introduction to SVA
• 25 June 2026 – Advanced Properties, Sequences & Auxiliary Logic
• 2 July 2026 – SVA Reuse, Formal Signoff & RISC-V Case Study

REGISTRATION FOR ALL 3 SESSIONS IS AT $60 ONLY.

Explore advanced SVA constructs, property semantics, sequence combinations, and auxiliary logic techniques used in modern verification environments.

Topics Covered

• Property semantics and evaluation regions

• Vacuous success and timing windows

• Parameterised properties

• Sequence repetition operators:

  • [*]

  • [=]

  • [->]

• Sequence combination operators:

  • and

  • or

  • intersect

  • throughout

  • within

  • first_match

• Auxiliary helper logic

• Mutex and race condition verification

• $onehot and parity checking

• ALU verification example

• VC Formal and Jasper Gold flows