On-Demand recordings access | Part 2++: RISC-V CPU Verification – Advanced | 3-Part RISC-V Verification Course +++

This is a part of a 3-session series:

• Part 1+++ – Introduction to CPU and CPU Verification - 16 April and 20-22 April 2026, 6.30 to 12.00
• Part 2+++ – RISC-V CPU Verification - 4 - 8 May 2026, 6.30 to 12.00
• Part 3+++ – RISC-V SoC Verification - 27-29 May and 1 June 2026, 6.30 to 12.00

REGISTRATION FOR ALL 3+++ SESSIONS IS AT £999 ONLY.

Part 2++ extends RISC-V CPU verification to advanced CPU-level strategies using multiple instruction stream generators (ISGs). Participants explore different instruction types, pipelines, microarchitectures, and caches, and gain hands-on experience with:

• Generating complex instruction streams using ISGs

• Applying advanced constraints and coverage models

• Optimising verification for varied CPU microarchitectures
  
  

This module builds real project-ready expertise, ensuring participants can confidently tackle RISC-V CPU verification in demanding environments.

What You’ll Gain

• Advanced ISG-based test generation for RISC-V CPUs

• Strategies for handling complex pipelines, caches, and microarchitectures

• Hands-on exercises reinforcing advanced CPU verification techniques

• VIP guidance for your own RISC-V CPU design

Agenda

• RISC-V CPU verification deep dive

• Advanced ISG techniques

• Microarchitecture-specific strategies

• Functional coverage and constraints modeling

• Classroom exercises and review