[3 sessions] AI in DV and VLSI

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Consists of the three sessions:

• 14 July 2026 3:00 to 5:00 pm – AI Methods in VLSI & DV
• 15 July 2026 3:00 to 5:00 pm – Benefits, Limitations & Case Studies
• 16 July 2026 3:00 to 5:00 pm – AI Flows, Deployment & Execution

This focused three-part series explores how AI is transforming VLSI design and Design Verification (DV) — from code generation to autonomous verification workflows.

Participants will gain a clear understanding of how AI can be applied today, what works in production, and how to safely deploy AI within verification environments.

Session Breakdown

Session 1 – AI Methods in VLSI & DV

• AI fundamentals: GenAI, ML, RL, Genetic Algorithms

• AI in VLSI design (auto-coding, linting, HLS acceleration)

• AI in DV: testbench generation, coverage optimisation, debug automation

Session 2 – Benefits, Limitations & Case Studies

• Real benefits: faster coding, improved coverage, reduced debug time

• Risks: hallucinations, IP security, compute costs

• Case studies:

  • Spec-to-UVM generation

  • Automated VLSI coding

• ROI and business case for AI adoption

Session 3 – AI Flows, Deployment & Execution

• Open-source vs enterprise AI tools

• Deployment on verification environments

• Integration with VCS and Xcelium

• Live workflow:
  Spec → UVM → Simulation → Debug → Self-correction

Learning Outcomes

By the end of the series, participants will:

• Understand how AI applies across VLSI and DV workflows

• Evaluate AI tools and deployment approaches

• Apply AI techniques to test generation, debug, and coverage

• Build a roadmap for AI adoption in verification teams