[3 parts] Functional Safety Verification

We offer 50% discount to students, please complete this form to avail discount.

Consists of the three sessions:

• 14-15 September 2026 1:00 to 5:00 pm – Safety Foundations & Block-Level Verification
• 16-17 September 2026 1:00 to 5:00 pm – CPU/Cluster-Level Safety
• 21-22 September 2026 1:00 to 5:00 pm – SoC-Level Full DV & ISO 26262 Evidence

Learn how modern functional safety mechanisms are architected, verified, and validated across block, CPU, and SoC levels for ISO 26262-compliant systems.

This live intensive training series explores how RTL safety mechanisms, fault injection, formal verification, FMEDA workflows, and safety sign-off methodologies are applied in real semiconductor and embedded systems development.

The programme focuses on:

• Functional safety fundamentals and ISO 26262 workflows

• ECC, parity, CRC, watchdogs, and safe-state architectures

• Fault injection and diagnostic coverage methodologies

• CPU lockstep and memory protection verification

• Formal property verification for safety mechanisms

• SoC-level fault management and escalation

• FMEDA evidence generation and safety closure

• Full-stack safety verification and compliance workflows

Designed for engineers working across automotive semiconductor development, RTL design verification, safety architecture, embedded systems, and ISO 26262 compliance.

What You Will Learn

By the end of this series, you will:

• Understand modern functional safety architectures and safety lifecycles

• Explore RTL safety mechanisms and diagnostic coverage methodologies

• Apply fault injection and formal verification workflows

• Understand CPU lockstep and cache ECC verification

• Learn how FMEDA evidence is generated from verification results

• Analyse SoC-level fault management and escalation architectures

• Build safety verification and ISO 26262 sign-off strategies

• Understand how safety mechanisms are validated across the full stack

Who Should Attend

• Functional Safety Engineers

• SoC & ASIC Verification Engineers

• RTL Design Engineers

• Automotive Semiconductor Engineers

• CPU & Safety Architects

• Embedded Systems Engineers

• UVM & Formal Verification Engineers

• ISO 26262 Compliance Teams

Course Structure

Part 1 — Safety Foundations & Block-Level Verification

Days 1–2

• Functional safety fundamentals and ISO 26262

• ECC, parity, CRC, and watchdog architectures

• Fault injection methodologies

• Safe reset and error reporting

• ASIL decomposition and FMEDA

• UVM safety verification workflows

• SVA-based safety assertions

• Safety verification reporting and closure

Part 2 — CPU/Cluster-Level Safety

Days 3–4

• Lockstep CPU architectures

• Cache ECC and memory scrubbing

• Register parity and TCM protection

• CPU-level SVA safety verification

• Formal property verification for safety mechanisms

• Clock, voltage, and thermal monitoring

• CPU-level FMEDA and diagnostic coverage

• Safe boot and CPU-level safety integration

Part 3 — SoC-Level Full DV & ISO 26262 Evidence

Days 5–6

• SoC safety architecture and verification strategy

• Safety Management Unit (SMU) verification

• Fault Collection Unit (FCU) and error routing

• Safe-state controllers and escalation

• SoC-level fault campaigns

• FMEDA evidence generation

• End-to-end secure and safe boot verification

• Full-stack safety closure and ISO 26262 sign-off

Training Format

• Live online instructor-led sessions

• 2 consecutive days per part

• 4 hours of training per day

• Interactive demonstrations and walkthroughs

• Real-world safety verification workflows

• Practical UVM, SVA, and fault injection methodologies

• Q&A and technical discussions

Key Benefits

✔ Learn practical ISO 26262 safety verification workflows
✔ Understand diagnostic coverage and FMEDA methodologies
✔ Explore ECC, lockstep, and fault management architectures
✔ Apply formal verification and fault injection techniques
✔ Gain insight into CPU and SoC-level safety sign-off
✔ Build end-to-end functional safety verification strategies