CPU/Cluster-Level Safety | Part 2: Functional Safety Verification

This session will be recorded and will be available to all registrants 1 week post-session.

Consists of the three sessions:

• 14-15 September 2026 1:00 to 5:00 pm – Safety Foundations & Block-Level Verification
• 16-17 September 2026 1:00 to 5:00 pm – CPU/Cluster-Level Safety
• 21-22 September 2026 1:00 to 5:00 pm – SoC-Level Full DV & ISO 26262 Evidence

Register for all 3 sessions of the series for only $150

2-Day Online Training

Format: Live Online
Duration: 2 Consecutive Days | 4 Hours per Day

Explore CPU-level functional safety architectures and verification workflows, including lockstep processors, cache ECC, memory protection, formal safety verification, and CPU-level FMEDA closure.

This intensive 2-day training focuses on how modern CPUs and safety clusters implement and verify diagnostic coverage and fault-tolerance mechanisms for ISO 26262 compliance.

What You Will Learn

By the end of this training, you will:

• Understand CPU lockstep safety architectures

• Explore cache ECC and memory scrubbing methodologies

• Learn register parity and TCM protection mechanisms

• Apply SVA and formal verification to safety mechanisms

• Understand monitor architectures and diagnostic coverage

• Generate FMEDA evidence from CPU-level verification workflows

• Analyse safe boot and CPU-level safety integration

Topics Covered

Day 3 — Lockstep, Cache ECC & CPU Safety Verification

• Lockstep CPU architectures

• Comparator verification methodologies

• Cache ECC and memory scrubbing

• UVM verification for cache ECC

• TCM protection and register parity

• Constrained-random safety verification

• CPU-level SVA safety assertions

• Assertion coverage methodologies

Day 4 — Formal Safety, Monitors & FMEDA Closure

• Formal property verification for safety

• Assume/assert/cover methodologies

• Clock, voltage, and thermal monitors

• Verification of monitor architectures

• CPU-level FMEDA workflows

• Diagnostic coverage computation

• Safe boot architectures

• CPU-level safety integration and sign-off

Who Should Attend

• CPU Verification Engineers

• Functional Safety Engineers

• RTL Designers

• Safety Architects

• UVM & Formal Verification Engineers

• Automotive Semiconductor Teams

Key Benefits

✔ Understand CPU-level safety architectures and verification
✔ Learn lockstep, ECC, and monitor verification methodologies
✔ Apply formal verification to safety mechanisms
✔ Explore FMEDA and diagnostic coverage workflows
✔ Gain practical insight into CPU safety sign-off strategies