Safety Foundations & Block-Level Verification | Part 1: Functional Safety Verification

This session will be recorded and will be available to all registrants 1 week post-session.

Consists of the three sessions:

• 14-15 September 2026 1:00 to 5:00 pm – Safety Foundations & Block-Level Verification
• 16-17 September 2026 1:00 to 5:00 pm – CPU/Cluster-Level Safety
• 21-22 September 2026 1:00 to 5:00 pm – SoC-Level Full DV & ISO 26262 Evidence

Register for all 3 sessions of the series for only $150

2-Day Online Training

Format: Live Online
Duration: 2 Consecutive Days | 4 Hours per Day

Build a strong foundation in functional safety verification, including ISO 26262 fundamentals, ECC and parity protection, watchdog architectures, fault injection methodologies, FMEDA workflows, and block-level safety verification strategies.

This intensive 2-day training explores how safety mechanisms are implemented and verified at the RTL and verification level within modern semiconductor systems.

What You Will Learn

By the end of this training, you will:

• Understand ISO 26262 functional safety fundamentals

• Explore ECC, parity, CRC, and watchdog architectures

• Learn diagnostic coverage and fault model methodologies

• Apply RTL fault injection and safety verification workflows

• Understand ASIL decomposition and FMEDA concepts

• Build UVM-based safety verification environments

• Learn structured safety reporting and sign-off approaches

Topics Covered

Day 1 — Fault Models, ECC & Error Detection

• Why functional safety fails in practice

• ISO 26262 and ASIL fundamentals

• ECC architecture and SECDED methodologies

• Fault injection for ECC verification

• Parity and CRC architectures

• Directed and constrained-random fault injection

• Watchdog architectures and FSM protection

• SVA assertions for safety mechanisms

Day 2 — Reset, FMEDA & Fault Infrastructure

• Safe reset controller architectures

• Error reporting and fault propagation

• ASIL decomposition methodologies

• FMEDA fundamentals and diagnostic coverage

• Fault injection infrastructure

• UVM fault injection environments

• Block-level safety verification planning

• Structured safety verification reporting

Who Should Attend

• Functional Safety Engineers

• RTL & ASIC Verification Engineers

• Automotive Semiconductor Engineers

• UVM Verification Engineers

• Safety Architects

• Embedded Systems Engineers

Key Benefits

✔ Learn practical block-level safety verification methodologies
✔ Understand ECC, parity, and watchdog safety architectures
✔ Explore fault injection and diagnostic coverage workflows
✔ Gain insight into FMEDA and ASIL verification strategies
✔ Build structured safety verification and reporting methodologies